1. Field of the Invention
The present invention relates to a network load reducing method and a node structure for a multiprocessor system with a distributed memory, and more particularly, to a method for reducing a data access time in a multiprocessor system with a distributed memory and a node structure for supporting the same.
2. Description of the Related Art
The recent development of semiconductor chip fabrication process technology has enabled the integration of a large amount of logic devices in a small area. However, the large amount of logic devices increases power consumption per chip. However, the increased power consumption is inconsistent with the market's requirements because mobile devices have emerged as the main application field of semiconductor system chips.
Accordingly, large-sized single-processor systems, depending on the development of process technology, are evolving into multiprocessor systems using a plurality of low-power small-sized processors.
FIG. 1 illustrates an example of a multiprocessor system with a two-dimensional mesh-based distributed memory.
Referring to FIG. 1, a multiprocessor system with a distributed memory includes a plurality of processors, switches and control devices.
The greatest problem in the implementation of the multiprocessor system is to secure the accessibility of data required by each processor. To this end, it is necessary to secure a high bandwidth for enabling the processors thereof to simultaneously access the same data storage, and it is necessary to enable two or more processors to use the same data if they access the same address region.
In the latter case, because most processors use a hierarchical memory structure, the problem is solved in the cache stage, known as a cache coherence scheme. The cache coherence scheme may be divided into a snooping-based cache coherence scheme and a directory-based cache coherence scheme.
The snooping-based cache coherence scheme is used in a bus-based multiprocessor system, which is suitable for a system that uses a small number of processors according to the bus characteristics thereof. On the other hand, the directory-based cache coherence scheme is used in a network-based multiprocessor system, which is applicable to a multiprocessor system due to its high extensibility.
When a node fails to read data stored in a cache, the directory-based cache coherence scheme causes a large amount of traffic, thus increasing the time taken to access data.